|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
high performance, 3.2 ghz, 14 - output jitter attenuator with jesd204b data sheet HMC7044 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed b y analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 C 2016 analog devices, in c. all rights reserved. technical support www.analog.com features ultralow rms jitter: 44 fs typical (12 khz to 20 mhz) at 2457.6 mhz noise floor: ?156 dbc/hz at 2457.6 mhz low phase noise: ?141.7 dbc/hz at 800 khz, 983.04 mhz output up to 14 lvds, lvpecl, or cml type device clocks (dclks) from pll2 maximum clkoutx/ clkoutx and sclkoutx/ sclkoutx frequency up to 3200 mhz jesd204b - compatible system reference (sysref) pulses 25 ps analog, and ? vco cycle dig ital delay independently programmable on each of 14 clock output channels spi - programmable phase noise vs. power consumption sysref valid interrupt to simplify jesd204b synchronization narrow - band, dual core vcos up to 2 buffered voltage controlled oscill ator (vcxo) outputs up to 4 input clocks in lvds, lvpecl, cmos, and cml modes frequency holdover mode to maintain output frequency loss of signal (los) detection and hitless reference switching 4 gpios alarms/status indicators to determine the health of the system external vco input to support up to 6000 mhz on - board regulators for excellent psrr 68- lead, 10 mm 10 mm lfcsp package applications jesd204b clock generation cellular infrastructure (multicarrier gsm, lte, w - cdma) data converter clocking microwave baseband cards phase array reference distribution general description the HMC7044 is a high performance , dual - loop , i nteger - n jitter attenuator capable of performing reference selection and generat ion of ultralow phase noise frequencies for high speed data converters with either parallel or serial (jesd204b type) interfaces. the HMC7044 features two integer mode plls and overlapping on - chip vcos that are spi - selectable with wide tuning ranges around 2.5 ghz and 3 ghz, respectively . the device is designed to meet the requirements of gsm and lte base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. the HMC7044 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different compo - nents including data converters, field - programmable gate arrays (fpgas), and mixer local oscillators (los). the dclk and sysref clock outputs of the HMC7044 can be configured to support signaling standards , such as cml, lvds, lvpecl , and lvcmos , and different bias settings to offset varying board insertion losses. functional block dia gram clkin0/rfsyncin clkin0/rfsyncin clkin1/fin clkin1/fin clkin2/oscout0 clkin2/oscout0 clkin3 clkin3 sync sdat a spi contro l inter f ace slen sclk 14-clock distribution pll1 pll2 sysref contro l clkout0 clkout0 sclkout1 sclkout1 clkout2 clkout2 sclkout3 sclkout3 clkout12 clkout12 sclkout13 sclkout13 cpout1 oscin oscin cpout2 oscout1 oscout1 13033-001 figure 1.
HMC7044 data she et rev. b | page 2 of 72 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 tabl e of contents .............................................................................. 2 revision history ............................................................................... 2 specifications ..................................................................................... 3 conditions ..................................................................................... 3 supply current .............................................................................. 3 digital input/output (i/o) electrical specifications ............... 4 pll1 characteristics .................................................................... 5 pll2 characteristics .................................................................... 7 vco char acteristics .................................................................... 8 clock output distribution characteristics ............................... 9 spur characteristics ................................................................... 10 noise and jitter characteristics ................................................ 10 clock output driver characteristics ....................................... 11 absolute maximum ratings .......................................................... 13 esd caution ................................................................................ 13 pin configuration and function descriptions ........................... 14 typical performance characteristics ........................................... 17 typical application circuits .......................................................... 21 terminology .................................................................................... 22 theory of operation ...................................................................... 23 detailed block diagram ............................................................ 24 dual pll overview .................................................................... 25 component blocks input pll (pll1) .................................. 25 component blocks output pll (pll2) .............................. 30 clock output network .............................................................. 31 reference buffer details ............................................................ 38 typical programming sequence ............................................... 38 power supply considerations ................................................... 39 serial control port ........................................................................ 42 serial port interface (spi) control ........................................... 42 applications information .............................................................. 43 pll1 noise calculations ........................................................... 43 pll2 noise calculations ........................................................... 43 phase noise floor and jitter ...................................................... 43 control registers ............................................................................ 44 control register map ................................................................ 44 control register map bit descriptions ................................... 52 evaluation pcb schematic ............................................................ 69 evaluation pcb ........................................................................... 69 outline dimensions ....................................................................... 71 ordering g uide .......................................................................... 71 revision history 1 1 /2016 rev. a to rev. b changes to table 1 and endnote 4, table 2 ................................... 3 changes to reliable signal swing parameter, table 4 .................. 5 change to pll2 vcxo input parameter, table 5 ........................ 7 changes to table 7 ............................................................................ 9 added figure 13; renumbered sequentially .............................. 18 added figure 20 .............................................................................. 19 added figure 21, figure 22, and figure 23 ................................. 20 changes to figure 34 ...................................................................... 21 changes to table 15 and table 17 ................................................ 34 changes to figure 47 ...................................................................... 3 7 changes to table 23 ........................................................................ 41 changes to table 25 ........................................................................ 4 6 changes to table 49 ........................................................................ 5 7 change to table 75 ......................................................................... 68 5 / 20 16 rev. 0 to rev. a changes to table 3 ............................................................................. 4 changes to current range (i cp2 ) parameter, table 5 .................... 8 changes to table 9 .......................................................................... 11 changes to table 10 ....................................................................... 13 changes to ldobyp5 pin description ...................................... 15 changes to figure 13 ...................................................................... 19 changes to figure 30 ...................................................................... 25 changes to evaluation pcb section ............................................ 69 added figure 46; renumbered sequentially .............................. 69 added figure 50 ............................................................................. 71 updated outline dimensions ....................................................... 71 9/ 20 15 revision 0: initial version data sheet HMC7044 rev. b | page 3 of 72 specifications unless otherwise noted, f vcxo = 122.88 mhz single - ended; clkin0/ clkin0 , clkin1/ clkin1 , clkin2/ clkin2 , and clkin3/ clkin3 differentia l at 122.88 mhz; f vco = 2949.12 mhz; doubler is on; typical value is given for v cc = 3.3 v; and t a = 25c. minimum and maximum values are given over the full v cc and t a (?40c to +85c) variation, as listed in table 1 . note that multifunction pins, such as clkin0/rfsyncin, are referred to either by the entire pin name or by a single function of the pin, for example, clkin0, when only that function is rele vant. conditions table 1 . parameter min typ max unit test conditions/comments supply voltage, v cc vcc1_vco 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for vco and vco distribution vcc2_out 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for output channel 2 and output channel 3 vcc3_sysref 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for common sysref divider vcc4_out 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for output channel 4, output channel 5, output channel 6, output channel 7 vcc5_pll1 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for the ldo used in pll1 vcc6_oscout 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for oscillator output path vcc7_pll2 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for the ldo used in pll2 vcc8_out 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for output channel 8, output channel 9, output channel 10, and output channel 11 vcc9_out 3.135 3.3 3.465 v 3.3 v 5%, supply voltage for output channel 0, output channel 1, output channel 12, and output channel 13 temperature ambient temperature range, t a ?40 +25 +85 c supply current for detailed test conditions, see table 22 and table 2 3 . table 2 . parameter 1 , 2 min typ max unit test conditions/comments current consumption 3 vcc1_vco 157 225 ma vcc2_out 4 65 250 ma typical value is given at t a = 25c with two lvds clocks at divide by 8 vcc3_sysref 12 37 ma vcc4_out 4 78 500 ma typical value is given at 25c with two lvpecl high performance clocks, fundamental frequency of internal vco (f o ), 2 sysref clocks (off ) vcc5_pll1 39 125 ma vcc6_oscout 0 80 ma vcc7_pll2 46 80 ma vcc8_out 4 124 500 ma typical value is given at 25c with two lvpecl high performance clocks at divide by 2, 2 sysref clocks (off ) vcc9_out 4 65 500 ma typical value is given at 25c with two lvds clocks at divide by 8, 2 sysref clocks (off ) total current 586 ma 1 maximum values are guaranteed by design and characterization. 2 currents include lvpecl termination currents. 3 max imum values are for all circuits enabled in their wor st case power consumption mode, pvt variations, and accounting for peak current draw during temporary synchronization events. 4 typi cal specification applies to a normal usage profile (profile 1 in table 2 3 ) , where pll1 and pll2 are locked, but very low duty cycle currents (sync events) and some optional features are disabled. this specification assumes output configurations as described in the test conditions/comments column. HMC7044 data sheet rev. b | page 4 of 72 digital input/output (i/o) electrical specifica tions table 3 . parameter min typ max unit test conditions/comments digital input signals (reset, sync, slen, sclk) safe input voltage range 1 ?0.1 +3.6 v input load 0.3 pf input voltage input logic high (v ih ) 1.2 v cc v input logic low (v il ) 0 0.5 v spi bus frequency 10 mhz digital bidirectional signals configured as inputs (sdata, gpio4, gpio3, gpio2, gpio1) safe input voltage range 1 ?0.1 +3.6 v input capacitance 0.4 pf input resistance 50g ? input voltage input logic high (v ih ) 1.22 v cc v input logic low (v il ) 0 0.24 v input hysteresis 0.2 v occurs around 0.85 v gpio1 to gpio4 alarm muxing/delay delay from internal alarm/signal to general - purpose output (gpo) driver 2 ns does not include t dgpo digital bidirectional signals configured as outputs (sdata, gpio4, gpio3, gpio2, gpio1) cmos mode logic 1 level 1.6 1.9 2.2 v logic 0 level 0 0.1 v output drive resistance (r drive ) 50 ? output driver delay (t dgpo ) 1.5 + 42 c load ns approximately 1.5 ns + 0.69 r drive c load (c load in nf) maximum supported dc current 1 0.6 ma open - drain mode 1 external 1 k ? pull - up resistor logic 1 level 3.6 v 3.6 v maximum permitted; specifications set by external supply logic 0 level 0.13 0.28 v against a 1 k ? external pull - up resistor to 3.3 v pull - down impedance 60 ? maximum supported sink current 5 ma 1 guaranteed by design and characterization . data sheet HMC7044 rev. b | page 5 of 72 pll1 characteristics table 4 . parameter min typ max unit test conditions/comments pll1 reference inputs (clkin0/ clkin0 , clkin1/ clkin1 , clkin2/ clkin2 , clkin3/ clkin3 ) reliable signal swing differential 0.375 1.4 v p - p differential, k eep signal at reference input pin <2.8 v, measured at 800 mhz single - ended 1 0.375 1.4 v p - p <250 mhz; keep signal at reference input pin <2.8 v common - mode range 0.4 2.4 v if user supplied, on - chip v cm is approximately 2.1 v input impedance 100 to 2000 ? user selectable; differential return loss ?12 db when terminated with 100 ? differentially pll1 reference divider 8 - bit lowest common multiple (lcm) dividers 1 255 16- bit r divider (r1) 1 65,535 pll1 feedback divider 16 - bit n divider (n1) 1 65,535 pll1 frequency limitations pll1 ref input frequency (f ref ) 0.00015 800 mhz minimum specification set by phase detector 1 (pd1) low limit digital los/lcm frequency (f lcm ) 0.00015 123 mhz typically run at about 38.4 mhz pd1 frequency (f pd1 ) 0.00015 50 mhz minimum specification = vcxo minimum frequency 65,535; 9.76 mhz typical pll1 charge pump charge pump current range (i cp1 ) 120 to 1920 a i cp1 from 0 to 15, vcxo control voltage (v tune ) = 1.4 v i cp1 variation over process voltage temperature (pvt) 15 % v tune = 1.4 v source/sink current mismatch 2 % source/sink mismatch at 1.4 v charge pump current step size 120 a charge pump compliance range 1 0.4 to 2.5 v i cp variation less than 10% 0.1 to 2.7 v maintain lock in test environment pll1 noise profile 1 floor figure of merit (fom) ?222 dbc/hz normalized to 1 hz flicker fom ?252 dbc/hz normalized to 1 hz flicker noise determined by formula 2 dbc/hz at f out , f offset noise floor determined by formula 3 dbc/hz at f out , f pd1 total phase noise (unfiltered) determined by formula 4 dbc/hz pll1 bandwidth and acquisition times 1 supported loop bandwidths (pll1_bw) 5 f lcm /2 25 f pd1 /10 hz typically pll1 low bw is set by the application and ranges between 5 hz and 2 khz pll1 slew time 6 n1/ f delta_vcxo sec n1 = 10 (typical) and f delta_vcxo = 10 khz (typical) results in 1 ms of slew time pll1 linear acquisition time 5/pll1_bw sec when vcxo has stopped slewing to steady state (within 5) pll1 phase error at pd1 invalidates lock 2.9 ns pll1 lock detect timer period (t lkd ) 7 4 to 2 26 t lcm user - selectable low phase error counts to declare lock HMC7044 data sheet rev. b | page 6 of 72 parameter min typ max unit test conditions/comments pll1 behavior on reference failure 1 los assertion delay 7 2 + t dgpo 3 + t dgpo t lcm from missing signal edge to alarm on gpo erroneously active i cp1 time on reference failure 8 0 8 ns temporary frequency glitch due to reference failure 0.03 ppm i cp1 = 1 ma, c12 = 4.6 nf, crystek cvpd -952 vcxo integrated frequency error due to reference failure 0.016 ppm i cp1 = 1 ma, c13 = 1 f, crystek cvpd - 952 vcxo signal valid time to clear los 9 2 3 t losval pll1 v tune leakage sources charge pump tristate leakage current 0.2 na board level xtal tune input port 0.5 na crystek cvpd - 952 vcxo board level loop filter components 2 na c12 = 4.6 nf, c13 = 1 f, r9 = 11 k ? , c15 = unpopulated holdover characteristics v tune drift over 1 sec in tristate mode 2 mv c12 = 4.6 nf, c13 = 1 f, r9 = 11 k ? , cvpd -950 vcxo holdover analog -to - digital converter (adc)/digital -to - analog converter (dac) resolution 19 mv 7 - bit, monotonic, no missing code adc/dac code 0 voltage 0.28 v adc/dac code 127 voltage 2.71 v dac temperature stability 0.07 mv/c at maximum code adc/dac integral nonlinearity (inl) ?0.11 lsbs worst case across codes holdoff timer period 1 , 10 1 2 26 t lcm holdover exit initial phase offsets 1 exit criteria = wait for low phase error the phase offset to make up after a transition from holdover to acquisition when using this feature exit action = none 4 ns exit criteria = any 11 exit action = reset dividers 1 2 t vcxo assumes n2 > 3 and dividers are reset upon exit; note that vcxo lags at start; value applies as the starting phase error if dac assisted release is used exit action = none n1 t vcxo dividers are not reset upon exit holdover exit characteristics 1 , 12 dac assisted release period per step (t dacassist ) 1/2 1/16 t lkd based on lock detect timer setpoint dac assisted release time 9 t dacassist time from decision to leave holdover until in fully natural acquisition; assumes no interruption by los or user delay of exit criteria 13 = wait for low phase error 14 n1/f err_vcxo sec data sheet HMC7044 rev. b | page 7 of 72 parameter min typ max unit test conditions/comments holdover exit frequency transients vs. mode peak frequency transient dac assisted release 2 ppm only available if using dac - based holdover 1 guaranteed by design and characterization. 2 see the pll1 noise calculations section f or more information on how to calculate the flicker noise for pll1. 3 see the pll1 noise calculations section for more information on how to calculate the noise floo r for pll1. 4 see the pll1 noise calculations section for more information on how to calculate the t otal phase n oise ( u nfiltered) for pll1. 5 set by external components. set the l ock detect threshold s ( pll1 lock detect timer[4:0] in register 0x0028) appropriately in the spi. 6 depends on initial phase offset (worst case is proportional to n1) and vcxo excess tuning range available over the targ et (f delta_vcxo ). for pfd rates typical of pll1, cycle slipping is normally insignificant. 7 t lcm is the least common multiple (lcm) of pll1 clock input frequencies. the specific ation is given in multiples of t lcm . 8 if los triggers before the pfd edge is normally detected (more likely with high r1 values), the charge pump is more likely to disable before the next invalid comparison occurs. otherwise, the fast tristate circuit disables the charge pump after about 4 ns (8 ns worst case) of phase error. 9 t l osval is a register value that is programmable from 1, 2, 4, , 64 t lcm . 10 if the hold off timer is used, the finite state machine ( fsm ) stays in holdover after los of the active reference before switching clocks, giving the original clock a chance to retur n. 11 t vcxo is the vcxo clock period. 12 see the pll1 holdover exit section. 13 the time required for the phases to intersect is inversely proportional to the holdover frequency error. note that the frequency error during holdover is expected to be much smalle r than is available from the tuning range of the vcxo. 14 f err_vcxo is the error frequency of the vcxo. pll2 characteristics table 5 . parameter min typ max unit test conditions/comments pll2 vcxo input recommended swing differential 0.2 1.4 v p -p differential, keep signal at oscin and oscin pins < 2.8 v single - ended (<250 mhz) 1 0.2 1.4 v p -p k eep signal at oscin and oscin pins < 2.8 v common - mode range 1.6 2.1 2.4 v if user supplied, on - chip v cm is approximately 2.1 v vcxo input slew rate 300 mv/ns slew rates as low as 100 mv/ns are functional, but can degrade the phase noise plateau by about 3 db input capacitance 1.5 pf per side; 3 pf differential differential input resistance 100 to 1000 ? user selectable return loss ?12 db when terminated with 100 ? differential pll2 external vco input recommended input power, ac - coupled differential ?6 6 dbm single - ended 1 ?6 6 dbm return loss ?12 db when terminated with 100 ? differential external vco frequency 1 400 3200 mhz fundamental mode; if < 1 ghz, set the low frequency external vco path bit (register 0x0064, bit 0) 400 6000 mhz using external vco 2 common - mode range 1 1.6 2.1 2.2 v pll2 dividers 12- bit reference divider range (r2) 1 4095 16- bit feedback divider range (n2) 8 65,535 pll2 frequency limitations vcxo frequency (f vcxo ) 10 500 mhz 122.88 mhz or 155 mhz are typical vcxo duty cycle using doubler 1 40 60 % distortion can lead to a spur at f pd /2 offset, note that minimum pulse width > 3 ns HMC7044 data sheet rev. b | page 8 of 72 parameter min typ max unit test conditions/comments reference doubler input frequency 10 175 mhz r2 input frequency 10 500 mhz pd2 frequency (f pd2 ) 0.00015 250 mhz recommended at high end of the range for best phase noise; typically 122.88 mhz 2 pll2 charge pump current range (i cp2 ) 160 to 2560 a i cp2 setting from 0 to 15 with 160 a step size, v tune = 1.4 v i cp2 variation over pvt 25 % v tune = 1.4 v source/sink current mismatch 2 % source/sink mismatch at 1.4 v current step size 160 a compliance range 0.3 to 2.45 v i cp variation less than 10% pll2 noise profile floor fom ?232 dbc/hz normalized to 1 hz flicker fom ?266 dbc/hz normalized to 1 hz fom variation vs. pvt 3 db fom degradation 3 db at minimum vcxo slew rate pll2 flicker noise determined by formula 2 dbc/hz at f out , f offset pll2 noise floor determined by formula 3 dbc/hz at f out , f pd2 pll2 total phase noise (unfiltered) determined by formula 4 dbc/hz pll2 bandwidth and acquisition times supported loop bandwidths (pll2_bw) 10 to 700 khz set by external components vco automatic gain control (agc) settling time 1 10 20 ms time from power - up of vco before initiating calibration; this applies to the 100 nf/1 f configuration of externa l decoupling capacitors on the vco supply network vco calibration time 5 2694 t pd2 n2 from 8 to 31 779 t pd2 n2 from 32 to 256 214 t pd2 n2 from 256 to 4095 139 t pd2 n2 > 4095 temperature range postcalibration 1 ?40 +85 c maintains lock from any temperature to any temperature pll2 linear acquisition time 5/pll2_bw sec after vcxo has stopped slewing to steady state pll2 lock detect timer period 5 512 t pd2 low phase error counts to declare lock 1 guaranteed by design and characterization. 2 see the pll2 noise calculations section for more information on how to calculate the flicker noise for pll2. 3 see the pll2 noise calculations section for more information on how to calculate the noise floor for pll2. 4 see the pll2 noise calculations section for more information on how to calculate the t otal phase n oise ( u nfiltered) for pll2. 5 t pd2 is the period of phase detector 2. vco characteristics table 6 . parameter min typ max unit test conditions/comments voltage controlled oscillator (vco) frequency tuning range, on - board vcos 1 2150 2880 mhz low vco typical coverage 2650 3550 mhz high vco typical coverage 2400 3200 mhz guaranteed frequency coverage 2 tuning sensitivity 38 to 44 mhz/v low frequency vco at 2457.6 mhz 35 to 40 mhz/v high frequency vco at 2949.12 mhz data sheet HMC7044 rev. b | page 9 of 72 parameter min typ max unit test conditions/comments open - loop vco phase noise f out = 2457.6 mhz f offset = 100 khz ?109 dbc/hz high performance mode, does not include floor contribution due to output network f offset = 800 khz ?134 dbc/hz f offset = 1 mhz ?136 dbc/hz f offset = 10 mhz ?156 dbc/hz normalized phase noise variation vs. frequency 2 db sweep across both vcos, all bands; normalize to 2457.6 mhz phase noise variation vs. temperature 2 db phase noise degradation in low performance mode 2 db 1 guaranteed by design and characterization. 2 although the device cover s this range without any gaps, for frequencies between ~2700 hz and 2900 hz, using a different vco core to synthesize the frequency can be required as process parameters shift. features are built into the HMC7044 to determine which core is selected for a given frequency that can fall in this range , but it can require software to configure these circuits appropriately. clock output distrib ution characteristic s table 7 . parameter min typ max unit test conditions/comments clock output skew clkoutx/ clkoutx to sclkoutx/ sclkoutx skew within one clock output pair 15 |ps| same pair, same type termination and configuration any clkoutx/ clkoutx to any sclkoutx/ sclkoutx 30 |ps| any pair, same type termination and configuration clock output divider 12- bit divider range 1 4094 1, 3, 5, and all even numbers up to 4094 sysref clock output divider 12- bit divider range 1 4094 1, 3, 5 and all even numbers up to 4094; pulse generator behavior is only supported for divide ratios 32 clock output analog fine delay analog fine delay adjustment range 1 135 670 ps 24 delay steps, f clkout = 983.04 mhz resolution 25 ps f clkout = 983.04 mhz (2949.12 mhz/3) maximum analog fine delay frequency 1 3200 mhz clock output coarse delay (flip flop based) coarse delay adjustment range 0 17 ? vco period 17 delay steps in ? vco period coarse delay resolution 169.54 ps f vco = 2949.12 mhz maximum frequency coarse delay 1 3200 mhz clock output coarse delay (slip based) coarse delay adjustment range 1 to vco period resolution 339.08 ps f vco = 2949.12 mhz maximum frequency coarse delay 1600 mhz 1 guaranteed by design and characterization. HMC7044 data sheet rev. b | page 10 of 72 spur characteristics table 8 . parameter min typ max unit test conditions/comments reference spur performance at 122.88 mhz and its harmonics ?70 dbc noise and jitter characteristics table 9 . parameter min typ max unit test conditions/comments closed - loop phase noise wide loop filter for best integrated noise ssb phase noise at 2457.6 mhz 1 ?98.0 dbc/hz offset = 100 hz ?111.1 dbc/hz offset = 1 khz ?119.8 dbc/hz offset = 10 khz ?125.2 dbc/hz offset = 100 khz ?126.9 dbc/hz offset = 300 khz ?131.3 dbc/hz offset = 1 mhz ?150.0 dbc/hz offset = 5 mhz ?154.0 dbc/hz offset = 10 mhz ?156.3 dbc/hz offset = 100 mhz 44.0 fs integrated jitter = 12 khz to 20 mhz at 614.4 mhz 1 ?110.4 dbc/hz offset = 100 hz ?122.8 dbc/hz offset = 1 khz ?131.3 dbc/hz offset = 10 khz ?136.6 dbc/hz offset = 100 khz ?138.3 dbc/hz offset = 300 khz ?142.7 dbc/hz offset = 1 mhz ?157.6 dbc/hz offset = 5 mhz ?158.8 dbc/hz offset = 10 mhz ?159.2 dbc/hz offset = 100 mhz 50.0 fs integrated jitter = 12 khz to 20 mhz closed - loop phase noise narrow loop filter for best 800 khz offset ssb phase noise at 2949.12 mhz 2 ?100.9 dbc/hz offset = 100 hz ?103.8 dbc/hz offset = 1 khz ?106.9 dbc/hz offset = 10 khz ?109.9 dbc/hz offset = 100 khz ?132.3 dbc/hz offset = 800 khz ?134.5 dbc/hz offset = 1 mhz ?152 dbc/hz offset = 10 mhz ?155.3 dbc/hz offset = 100 mhz 108 fs integrated jitter = 12 khz to 20 mhz at 983.04 mhz 2 ?110.4 dbc/hz offset = 100 hz ?113.3 dbc/hz offset = 1 khz ?116.4 dbc/hz offset = 10 khz ?119.4 dbc/hz offset = 100 khz ?141.7 dbc/hz offset = 800 khz ?143.7 dbc/hz offset = 1 mhz ?157.1 dbc/hz offset = 10 mhz data sheet HMC7044 rev. b | page 11 of 72 parameter min typ max unit test conditions/comments ?157.1 dbc/hz offset = 100 mhz 102 fs integrated jitter 12 khz to 20 mhz output network floor fom cml with 100 ? internal termination (cml100) fundamental mode ?250 dbc/hz high performance divide by 1 to divide by n ?248 dbc/hz high performance divide by 1 to divide by n ?247 dbc/hz low power (4 db less power) lvpecl fundamental mode ?250 dbc/hz divide by 1 to divide by n ?247 dbc/hz lvds divide by 1 to divide by n ?244 dbc/hz high performance divide by 1 to divide by n ?243 dbc/hz low power (4 db less power) phase noise degredation due to harmonics 3 fundamental only 0.00 db third harmonic 0.25 db third and fifth harmonics 0.40 db third, fifth, and seventh harmonics 0.50 db third, fifth, seventh, and ninth harmonics 0.53 db third through 61 st harmonics 0.64 db phase noise floor and jitter phase noise floor at f out determined by formula 4 dbc/hz jitter density of floor at f out determined by formula 5 sec/hz rms additive jitter due to floor determined by formula 6 sec from f out and output channel fom 1 pll2 l ocked at 122.88 mhz 2 10, wide (600 khz) l oop f ilter for best 12 k hz to 20 m hz jitter , cml100 h igh p erformance output buffer. 2 pll2 locked at 122.88 mhz 2 12, narrow loop for best 800 hz offset, cml100 high performance output buffer. 3 when the harmonics o f the signal are captured in the measurement bandwidth of the receiving instrument/circuit, the noise power of those harmonic s can fold and influence the overall noise. their presence causes a decibel for decibel influence. f or example, if the third harmon ic is at ? 10 dbc, there is an additional noise contributor of 10 db lower than the fundamental at all offsets that folds in - band and causes a 0.2 db hit overall. the influence of the harmonics factoring into the degradation is primarily a function of the frequency of the buffer bandwidth relative to the third , fifth , and se venth harmonics. as the output frequency reduces, more harmonics fall into the observation bandwidth, and the degradation worsens, but only slightly. this ef fect produces a penalty of 0.65 db maximum if harmonics u p to the 61 st harmonic is included . 4 see the phase noise floor and jitter section for more information on how to calculate the phase noise floor. 5 see the phase noise floor and jitter section for more information on how to calculate the j itter density of floor . 6 see the phase noise floor and jitter section for more information on how to calculate the rms additive jitter due to floor. clock output driver characteristics table 10. parameter min typ max unit test conditions/comments cml mode (low power) r l = 100 ? , 9.6 ma ?3 db bandwidth 1950 mhz differential output voltage = 980 mv p - p diff output rise time 175 ps f clkout = 245.76 mhz, 20% to 80% 145 ps f clkout = 983.04 mhz, 20% to 80% output fall time 185 ps f clkout = 245.76 mhz, 20% to 80% 145 ps f clkout = 983.04 mhz, 20% to 80% output duty cycle 1 47.5 50 52.5 % f clkout = 1075 mhz (2150 mhz/2) differential output voltage magnitude 1390 mv p - p diff f clkout = 245.76 mhz (2949.12 mhz/12) 1360 mv p - p diff f clkout = 983.04 mhz (2949.12 mhz/3) common - mode output voltage v cc ? 1.05 v f clkout = 245.76 mhz (2949.12 mhz/12) cml mode (high power) r l = 100 ? , 14.5 ma 3 db bandwidth 1400 mhz differential output voltage = 1410 mv p - p diff output rise time 250 ps f clkout = 245.76 mhz, 20% to 80% 165 ps f clkout = 983.04 mhz, 20% to 80% output fall time 255 ps f clkout = 245.76 mhz, 20% to 80% 170 ps f clkout = 983.04 mhz, 20% to 80% HMC7044 data sheet rev. b | page 12 of 72 parameter min typ max unit test conditions/comments output duty cycle 1 47.5 50 52.5 % f clkout = 1075 mhz (2150 mhz/2) differential output voltage magnitude 2000 mv p - p diff f clkout = 245.76 mhz (2949.12 mhz/12) 1800 mv p - p diff f clkout = 983.04 mhz (2949.12 mhz/3) common - mode output voltage v cc ? 1.6 v f clkout = 245.76 mhz (2949.12 mhz/12) lvpecl mode r l = 150 ? , 4.8 ma 3 db bandwidth 2400 mhz differential output voltage = 1240 mv p - p diff output rise time 135 ps f clkout = 245.76 mhz, 20% to 80% 130 ps f clkout = 983.04 mhz, 20% to 80% output fall time 135 ps f clkout = 245.76 mhz, 20% to 80% 130 ps f clkout = 983.04 mhz, 20% to 80% output duty cycle 1 47.5 50 52.5 % f clkout = 1075 mhz (2150 mhz/2) differential output voltage magnitude 1760 mv p - p diff f clkout = 245.76 mhz (2949.12 mhz/12) 1850 mv p - p diff f clkout = 983.04 mhz (2949.12 mhz/3) common - mode output voltage v cc ? 1.3 v f clkout = 245.76 mhz (2949.12 mhz/12) lvds mode (low power) 1.75 ma maximum operating frequency 600 mhz differential output voltage = 400 mv p - p diff output rise time 135 ps f clkout = 245.76 mhz, 20% to 80% 100 ps f clkout = 983.04 mhz, 20% to 80% output fall time 135 ps f clkout = 245.76 mhz, 20% to 80% 95 ps f clkout = 983.04 mhz, 20% to 80% output duty cycle 1 47.5 50 52.5 % f clkout = 1075 mhz (2150 mhz/2) differential output voltage magnitude 390 mv p - p diff f clkout = 245.76 mhz (2949.12 mhz/12) common - mode output voltage 1.1 v f clkout = 245.76 mhz (2949.12 mhz/12) lvds mode (high power) 3.5 ma maximum operating frequency 1700 mhz differential output voltage = 650 mv p - p diff output rise time 145 ps f clkout = 245.76 mhz, 20% to 80% 105 ps f clkout = 983.04 mhz, 20% to 80% output fall time 145 ps f clkout = 245.76 mhz, 20% to 80% 100 ps f clkout = 983.04 mhz, 20% to 80% output duty cycle 1 47.5 50 52.5 % f clkout = 1075 mhz (2150 mhz/2) differential output voltage magnitude 750 mv p - p diff f clkout = 245.76 mhz (2949.12 mhz/12) 730 mv p - p diff f clkout = 983.04 mhz (2949.12 mhz/3) common - mode output voltage 1.1 v f clkout = 245.76 mhz (2949.12 mhz/12) cmos mode maximum operating frequency 600 mhz single - ended output voltage = 940 mv p - p diff output rise time 425 ps f clkout = 245.76 mhz, 20% to 80% output fall time 420 ps f clkout = 245.76 mhz, 20% to 80% output duty cycle 1 47.5 50 52.5 % f clkout = 1075 mhz (2150 mhz/2) output voltage high v cc ? 0.07 v load current = 1 ma v cc ? 0.5 v load current = 10 ma output 0.07 v load current = 1 ma 0.5 v load current = 10 ma 1 guaranteed by design and characterization. data sheet HMC7044 rev. b | page 13 of 72 absolute maximum rat ings table 11. parameter rating vcc1 _vco , vcc2 _out , vcc3 _sysref , vcc4 _out , vcc5 _pll1 , vcc6 _oscout , vcc7 _pll2 , vcc8 _out , vcc9 _out ? 0.3 v to +3.6 v maximum junction temperature (t j ) 125c maximum peak reflow temperature 260c thermal resistance ( channel to ground paddle ) 7c/w storage temperature range ? 65c to +150c operating temperature range ? 40c to +85c esd sensitivity level human body model class 1c charged device model 1 class 3 1 per jesd22 - c101 - f (cdm) standard. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caut ion HMC7044 data sheet rev. b | page 14 of 72 pin configuration an d function descripti ons 13033-002 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 clkout0 notes 1. exposed p ad. connect the exposed p ad t o a high qualit y rf/dc ground. clkout0 sclkout1 sclkout1 reset sync bgabyp1 ldobyp2 ldobyp3 vcc1_vco ldobyp4 ldobyp5 sclkout3 sclkout3 clkout2 clkout2 17 vcc2_out 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 vcc7_pll2 cpout2 ldobyp7 oscin oscin ldobyp6 oscout1 oscout1 clkin2/oscout0 clkin2/oscout0 vcc6_oscout clkin0/rfsyncin clkin0/rfsyncin vcc5_pll1 clkin1/fin clkin1/fin 35 rsv 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 slen sclk sdat a vcc3_sysref sclkout5 sclkout5 clkout4 clkout4 vcc4_out clkout6 clkout6 sclkout7 sclkout7 gpio1 cpout1 clkin3 34 clkin3 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 vcc9_out clkout12 clkout12 sclkout13 sclkout13 gpio4 gpio3 sclkout 1 1 sclkout 1 1 clkout10 clkout10 vcc8_out clkout8 clkout8 sclkout9 sclkout9 52 gpio2 HMC7044 t op view (not to scale) figure 2 . pin configuration table 12 . pin function descriptions pin no. mnemonic type 1 description 1 clkout0 o true clock output channel 0 . default dclk profile. 2 clkout0 o complementary clock output channel 0 . default dclk profile. 3 sclkout1 o true clock output channel 1. default sysref profile. 4 sclkout1 o complementary clock output channel 1. default sysref profile. 5 reset i device reset input. active high. for normal operation, set reset to 0. 6 sync i synchronization input. this pin is used for multichip synchronization. if not used, set sync to 0. 7 bgabyp1 band gap bypass capacitor connection. connect a 4.7 f capacitor to ground. this pin affects all internally regulated supplies. 8 ldobyp2 ldo bypass 2. connect a 4.7 f capacitor to ground . the internal digital supply is 1.8 v. this pin is the ldo bypass for the pll1, pll2, and sysref sections. 9 ldobyp3 ldo bypass 3. connect a 4.7 f capacitor to ground . this pin is the 2.8 v supply to pll1, phase frequency detector 1 (pfd1), charge pum p 1 (cp1), rf synchronization (rfsync), and pin 36 buffers. 10 vcc1_vco p 3.3 v supply for vco and vco distribution. 11 ldobyp4 ldo bypass 4. connect a 1 f capacitor to ground. this pin is the first stage regulator for the vco supply. 12 ldobyp5 ldo bypass 5. connect a 100 n f capacitor to ldobyp4. this pin is the vco core supply voltage. 13 sclkout3 o true clock output channel 3. default sysref profile. 14 sclkout3 o complementary clock output channel 3. default sysref profile. 15 clkout2 o true clock output channel 2. default dclk profile. 16 clkout2 o complementary clock output channel 2. default dclk profile. 17 vcc2_out p power supply for clock group 1 (southwest) channel 2 and channel 3. see the clock grouping, ske w, and crosstalk section. 18 slen i spi latch enable . data sheet HMC7044 rev. b | page 15 of 72 pin no. mnemonic type 1 description 19 sclk i spi clock. 20 sdata i/o spi data. 21 vcc3_sysref p power supply for common sysref divider. 22 sclkout5 o true clock output channel 5. default sysref profile. 23 sclkout5 o complementary clock output channel 5. default sysref profile. 24 clkout4 o true clock output channel 4. default dclk profile. 25 clkout4 o complementary clock output channel 4. default dclk profile. 26 vcc4_out p power supply for clock group 2 (south) channel 4 , channel 5, channel 6, and channel 7. see the clock grouping, ske w, and crosstalk section. 27 clkout6 o true clock output channel 6. default dclk profile. 28 clkout6 o complementary clock output channel 6. default dclk profile. 29 sclkout7 o true clock output channel 7. default sysref profile. 30 sclkout7 o complementary clock output channel 7. default sysref profile. 31 gpio1 i/o programmable general - purpose input / output 1. 32 cpout1 o pll1 charge pump output. 33 clkin3 i true reference clock input 3 of pll1 . 34 clkin3 i complementary reference clock input 3 of pll1 . 35 rsv r reserved pin. this pin must be tied to ground. 36 clkin1/fin i true reference clock input 1 of pll1 / external vco input for external vco mode. 37 clkin1 / fin i complementary reference clock input 1 of pll1 /complementary external vco input for external vco mode. 38 vcc5_pll1 p power supply for ldo, used for pll1 . 39 clkin0/rfsyncin i true reference clock input 0 of pll1 / rf synchronization input with deterministic delay. 40 clkin0 / rfsyncin i complementary reference clock input 0 of pll1 /complementary rf synchronization input with deterministic delay. 41 vcc6_oscout p power supply for oscillator output path. 42 clkin2/oscout0 i/o true reference clock input 2 (bidirectional pin ) of pll1 /buffered output 0 of oscillator input. 43 clkin2 / oscout0 i/o complementary reference clock input 2 (bidirectional pin ) of pll1 /complementary buffered output 0 of oscillator input. 44 oscout1 o true buffered output 1 of oscillator input. 45 oscout1 o complementary buffered output 1 of oscillator i nput. 46 ldobyp6 ldo bypass , connect a 4.7 f capacitor to ground . this pin is the ldo bypass for r2, n2, phase frequency detector 2 (pfd2), charge pump 2 (cp2), and the pll2 loop filter. 47 oscin i true feedback input to pll1. this pin is a r eference input to pll2 . 48 oscin i complementary feedback input to pll1. this pin is a r eference input to pll2 . 49 ldobyp7 ldo bypass. connect a 4.7 f capacitor to ground . this pin is the ldo bypass for the vcxo buffer and frequency doubler os cillator output divider. 50 cpout2 i/o pll2 charge pump output. 51 vcc7_pll2 p p ower supply for ldo for pll2 . 52 gpio2 i/o programmable general - purpose input/output 2. 53 sclkout9 o true clock output channel 9. default sysref profile. 54 sclkout9 o complementary clock output channel 9. default sysref profile. 55 clkout8 o true clock output channel 8. default dclk profile. 56 clkout8 o complementary clock output channel 8. default dclk profile. 57 vcc8_out p power supply for clock group 3 (north) channel 8 , channel 9, channel 10, and channel 11. see the clock grouping, ske w, and crosstalk section. 58 clkout10 o true clock output channel 10. default dclk profile. 59 clkout10 o complementary clock output channel 10. default dclk profile. 60 sclkout11 o true clock output channel 11. default sysref profile. 61 sclkout11 o complementary clock output channel 11. default sysref profile. 62 gpio3 i/o programmable general - purpose input/output 3. sleep input by default. 63 gpio4 i/o programmable general - purpose input/output 4. pulse generator request by default. 64 sclkout13 o true clock output channel 13. default sysref profile. HMC7044 data sheet rev. b | page 16 of 72 pin no. mnemonic type 1 description 65 sclkout13 o complementary clock output channel 13. default sysref profile. 66 clkout12 o true clock output channel 12. default dclk profile. 67 clkout12 o complementary clock output channel 12. default dclk profile. 68 vcc9_out p power supply for clock group 0 (northwest) channel 0, channel 1 , channel 12, and channel 13. see the clock grouping, ske w, and crosstalk section. ep exposed pad. connect the exposed pad to a high quality rf/dc ground. 1 o is output, i is input, p is power, and i/o is input/out put. data sheet HMC7044 rev. b | page 17 of 72 typical performance characteristics unless otherwise noted, pfd pll1 = 7.68 mhz, pfd pll2 = 122.88 mhz 2; i cp1 = 1.92 ma, i cp2 = 2.56 ma (wide loop), i cp2 = 1.12 ma (narrow loop), pll1 loop bw ~ 70 hz, pll2 wide loop bw 650 khz, pll2 narrow loop bw 215 khz, pll2 narrow loop filter = 1.1 nf | 160 33 nf; pll2 wide loop filter = 150 pf | 430 4.7 nf; pll1 loop filter = 4.7 nf | 10 f 1.2 k. ?70 ?60 ?50 ?40 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?180 ?170 100 10 1 1k 10k 100k 1m 10m 13033-003 phase noise (dbc/hz) frequency (hz) noise: analysis range x: band marker analysis range y: band marker intg noise: ?66dbc/20mhz rms noise: 696rad 0.004 rms jitter: 45fs residual fm: 1.6khz 3 4 5 1 2 1: 1khz, ?107.8dbc/hz 2: 10khz, ?119.5dbc/hz 3: 100khz, ?124.7dbc/hz 4: 1mhz, ?131.5bc/hz 5: 10mhz, ?153.1dbc/hz 6: 20mhz, ?154.4dbc/hz 7: 20mhz, ?154.4dbc/hz x: start 12khz stop 20mhz center 10mhz span 20mhz pll1 cascaded pll1 + pll2 6 7 figure 3. cascaded phase noise at 2457.6 mhz, pll2 wide loop bandwidth ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 1k 10k 100k 1m 10m 13033-005 phase noise (dbc/hz) frequency (hz) 1: 1khz, ?105.3dbc/hz 2: 10khz, ?108.5dbc/hz 3: 100khz, ?111.4dbc/hz 4: 800khz, ?134.2dbc/hz 5: 1mhz, ?136.5dbc/hz 6: 10mhz, ?153.3dbc/hz 7: 20mhz, ?154.6dbc/hz x: start 12khz stop 20mhz center 10mhz span 20mhz wide loop narrow loop 3 4 5 6 2 noise: analysis range x: band marker analysis range y: band marker intg noise: ?56.9dbc/20mhz rms noise: 2.0rad .116 rms jitter: 131fs residual fm: 1.5khz 7 1 figure 4. phase noise at 2457.6 mhz, narrow vs. pll2 wide loop bandwidth ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 100 1k 10k 100k 1m 10m 13033-004 phase noise (dbc/hz) frequency (hz) 1: 1khz, ?110.4dbc/hz 2: 10khz, ?120.0dbc/hz 3: 100khz, ?124.9dbc/hz 4: 1mhz, ?131.2dbc/hz 5: 10mhz, ?153.2dbc/hz 6: 20mhz, ?154.5dbc/hz 7: 20mhz, ?154.5dbc/hz x: start 12khz stop 20mhz center 10mhz span 20mhz noise: analysis range x: band marker analysis range y: band marker intg noise: ?66.1dbc/20.0mhz rms noise: 702rad .040 rms jitter: 45fs residual fm: 1.6khz 3 4 5 2 crystek vcxo wenzel vcxo 1 6 7 figure 5. pll2 phase noise vs. frequency, vcxo quality at 2457.6 mhz, w ide loop bandwidth ?160 ?150 ?140 ?130 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 1 10 100 1k 10k 100k 1m phase noise (dbc/hz) frequenc y (hz) t o t a l p l l 1 n o i s e (simul a ted) p f d /c p n o i s e (simul a ted) w e n z e l r e f (simul a ted) v cxo (simul a ted) t o t a l p l l 1 n o i s e (measured) 13033-008 figure 6. closed - loop phase noise at 122.88 mhz, pll1 measurement vs. simulated, clean reference source, ~70 hz loop bandwidth 80 phase margin ?160 ?150 ?140 ?130 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 1 10 100 1k 10k 100k phase noise (dbc/hz) frequenc y (hz) t o t al p l l 1 output (simul a ted) p f d /c p n o i s e (simul a ted) nois y source (simul a ted) v cxo (simul a ted) nois y source, open loo p (measured) t o t al p l l 1 n o i s e (measured) 13033-009 figure 7 . closed - loop phase noise a t 122.88 mhz, pll1 measurement vs. simulated, noisy reference source, ~70 hz loop bandwidth, 80 phase margin ?170 ?165 ?160 ?155 ?150 ?145 ?140 ?135 ?130 ?125 ?120 100 600 1 100 1600 2100 2600 3100 3600 phase noise (dbc/hz) frequenc y (mhz) 800 k hz w i d e l o o p 800 k hz n ar r o w l o o p 20log ( 800 k hz w i d e l o o p ) 20log ( 800 k hz n ar r o w l o o p ) 13033-006 figure 8 . phase noise vs. frequency at common output frequencies HMC7044 data sheet rev. b | page 18 of 72 0 20 40 60 80 100 120 140 160 100 600 1 100 1600 2100 2600 3100 3600 jitetr (fs) frequenc y (mhz) jitter w i d e l o o p jitter n a r r o w l o o p 13033-007 figure 9. 12 khz to 20 mhz jitter vs. frequency, wide loop and narrow loop at common output frequencies ?105 ?100 ?95 ?90 ?110 ?115 ?120 ?125 ?130 ?135 ?140 ?145 ?150 ?160 ?155 100 1k 10k 100k 1m 10m 13033-021 phase noise (dbc/hz) frequency (hz) noise: analysis range x: band marker analysis range y: band marker intg noise: ?66.4dbc/20mhz rms noise: 678rad .039 rms jitter: 44fs residual fm: 1.5khz 5 6 7 1 2 3 4 8: 100hz, ?99.8dbc/hz 1: 1khz, ?111.1dbc/hz 2: 10khz, ?119.8dbc/hz 3: 100khz, ?125.2dbc/hz 7: 300khz, ?126.9dbc/hz 4: 1mhz, ?131.3bc/hz 5: 10mhz, ?153.1dbc/hz 6: 32.8mhz, ?156.3dbc/hz x: start 12khz stop 20mhz center 10mhz span 20mhz 8 figure 10 . phase noise, clkoutx/ clkoutx = 2457.6 mhz, optimized for best integrated jitter (12 khz to 20 mhz) 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 k vco (mhz/v) vco v tune (v) 2865 . 72 m h z 3511 . 86 m h z 2115 . 38 m h z 2627 . 75 5 m h z c a p = 0 l o w v co c a p = 31 l o w v co c a p = 0 h i g h v co c a p = 31 h i g h v co 13033-010 figure 11 . vco gain (k vco ) vs. vco v tune 0 0.5 1.0 1.5 2.0 2.5 3.0 2050 2250 2450 2650 2850 3050 3250 3450 3650 vco v tune (v) frequenc y (mhz) l o w v c o ?40c l o w v c o + 25c l o w v c o + 85c h ig h v c o ?40c h ig h v c o + 25c h ig h v c o + 85c 13033-011 figure 12 . vco v tune vs. frequency 100m 1g 3g differentia l output vo lt age (v p-p diff) frequenc y (hz) 13033-112 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 l v p e cl cm l 100 h igh cm l 100 l o w l v d s high cm o s (not in differentia l mode) figure 13 . differential output voltage vs. frequency at different modes differentia l output vo lt age (v p-p diff) frequenc y (ghz) 13033-012 0 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35 1.50 1.65 1.80 1.95 2.10 2.25 1.0 1.5 2.0 2.5 3.0 3.5 l v p e cl cm l 100 h igh cm l 100 l o w l v d s high figure 14 . differential output voltage vs. frequency at different modes data sheet HMC7044 rev. b | page 19 of 72 100m 1g 3g differentia l output power (v p-p diff) 13033-013 frequenc y (hz) ?40c + 25c + 85c 0 0.5 1.0 1.5 2.0 2.5 figure 15 . lvpecl differential output voltage vs. frequency at different temperatures ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 0.4 0.8 1.2 1.6 2.0 clkout0/clkout0 vo lt age (v) time (ns) 13033-017 figure 16 . differential clkout0/ clkout0 at 2457 mhz, lvpecl ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 1 2 3 4 5 6 7 8 9 10 time (ns) 13033-018 clkout0/clkout0 vo lt age (v) figure 17 . differential clkout0/ clkout0 voltage at 614.4 mhz, lvpecl 10 15 20 25 30 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 del a y ste p size (ps) del a y ste p ?40c + 25c + 85c 13033-020 figure 18 . analog delay step size vs. delay step over temperature, lvpecl at 1474.56 mhz ?200 ?100 0 100 200 300 400 500 600 700 800 fund dis 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 analog del a y (ps) del a y setting ?40c + 25c + 85c 13033-019 fund: fundamen t al mode a t 2949mhz dis: analog del a y is disabled a t 1474mhz figure 19 . analog delay vs. delay setting over temperature, lvpecl at 1474.56 mhz 0 5 10 15 20 25 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 delay step size (ps) delay step ?40c + 25c + 85c 13033-119 figure 20 . analog delay step size vs delay step over temperature, lvpecl at 3072 mhz with digital delay = 0 HMC7044 data sheet rev. b | page 20 of 72 0 100 200 300 400 500 600 700 a n a log d e l a y ( p s) d e l a y s e tt i n g 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 24 ?40c + 25c + 85c 13033-120 figure 21 . analog delay vs. delay setting over temperature, lvpecl at 3072 mhz with digital delay = 0 10 15 20 25 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 delay step size (ps) delay step ?40c + 25c + 85c 13033-121 figure 22 . analog delay step size vs delay step over temperature, lvpecl at 3072 mhz with digital delay = 1 0 100 200 300 400 500 600 800 700 a n a log d e l a y ( p s) d e l a y s e tt i n g 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 24 ?40c + 25c + 85c 13033-122 figure 23 . analog delay vs. delay setting over temperature, lvpecl at 3072 mhz with digital delay = 1 ?0.5 0 0.5 1.0 1.5 2.0 2.5 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0 200 400 600 800 1000 clock grou p v alid phase alarm vo lt age (v) clock ouput vo lt age (v) time (ns) clkout0 clkout2 valid phase alarm 13033-014 figure 24 . output channel synchronization before and after rephase ?0.5 0 0.5 1.0 1.5 2.0 2.5 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 330 335 340 345 350 clock grou p v alid phase alarm vo lt age (v) clock output vo lt age (v) time (ns) clkout0 clkout2 valid phase alarm 13033-015 figure 25 . output channel synchronization before rephase ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 695 700 705 710 715 clock grou p v alid phase alarm vo lt age (v) clock output vo lt age (v) time (ns) clkout0 clkout2 valid phase alarm 13033-016 ?0.5 0 0.5 1.0 1.5 2.0 2.5 figure 26 . output channel synchronization after rephase data sheet HMC7044 rev. b | page 21 of 72 typical application circuits 100? 0.1f 0.1f downstream device l vds output high impedance input HMC7044 13033-022 figure 27 . ac - coupled lvds output driver 0.1f 0.1f downstream device cm l output high impedance input 13033-028 HMC7044 100? 100? vcc 100? 0.1f 0.1f downstream device cm l output high impedance input 13033-026 HMC7044 100? 100? vccx_out 100? 0.1f 0.1f self biased re f , vcxo inputs 13033-030 HMC7044 figure 30 . clkin0/ clkin0 , clkin1/ clkin1 , clkin2/ clkin2 , clkin3/ clkin3 , and oscin/ oscin input, differential mode 100? downstream device l vds output high impedance input 13033-023 HMC7044 figure 31 . dc - coupled lvds output driver downstream device ( l vpecl) l vpecl- com pa tible output 13033-025 HMC7044 50? 50? 50? gnd figure 32 . dc - coupled lvpecl output driver cm l output HMC7044 100? 100? vccx_out 13033-027 downstream device (cml) figure 33 . dc - coupled cml (internal) output driver 0.1f 13033-031 HMC7044 3.3v driver 47? HMC7044 data sheet rev. b | page 22 of 72 terminology phase jitter an ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. actual signals, however, display a certain amount of variation from i deal phase progression over time. this phenomenon is phase jitter. although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being gaussian (normal) in distribution. this phase jitter lead s to the energy of the sine wave in the frequency domain spreading out, producing a continuous power spectrum. this power spectrum is usually reported as a series of values whose units are dbc/hz at a given offset in frequency from the sine wave (carrier). the value is a ratio (expressed in decibels) of the power contained within a 1 hz bandwidth with respect to the power at the carrier frequency. for each measurement, the offset from the carrier frequency is also given. phase noise it is meaningful to in tegrate the total power contained within some interval of offset frequencies (for example, 10 khz to 10 mhz). this is the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. phase noise has a detrimental effect on the performance of adcs , dacs, and rf mixers. it lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. time jitter phase noise is a frequency domain phenomenon. in the time domain, the same effect is exhibited as time jitter. when observing a sine wave, the time of successive zero crossings varies. in a square wave, the time jitter is a displacement of the edges from t heir ideal (regular) times of occurrence. in both cases, the variations in timing from the ideal are the time jitter. because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma of the gaussian d istribution. time jitter that occurs on a sampling clock for a dac or an adc decreases the signal - to - noise ratio (snr) and dynamic range of the converter. a sampling clock with the lowest possible jitter provides the highest performance from a given conver ter. additive phase noise additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. the phase noise of any external oscillators or clock sources is subtracted, which makes it possible to predict the d egree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. in many cases, the phase noise of one element dominates the system phase noise. when there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. additive time jitter additive time jitter is the amount of time jitter that is attributable to the d evice or subsystem being measured. the time jitter of any external oscillators or clock sources is subtracted, which makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. in many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. data sheet HMC7044 rev. b | page 23 of 72 theory of operation the HMC7044 is a high performance, dual - loop, integer n jitter attenuator capable of performing frequency translation, reference sele ction, and generation of ultralow phase noise references for high speed data converters with either parallel or serial (jesd204b type) interfaces. the device is designed to meet the requirements of demanding base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. the HMC7044 uses a dual - loo p architecture, where two integer mode plls are connected in series to form a jitter attenuating clock multiplier unit. the high performance dual - loop topology of the HMC7044 enables the wireless/rf system designer to attenuate the incoming jitter of a primary system reference clock (for example, common public radio interface? (cpri) source) and generate low phase noise, high freq uency clocks to drive data converter sample clock inputs. the HMC7044 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components in a n rf trans - ceiver system, such as data converters, local oscillators, transmit/receive modules, fpgas , and digital front - end (dfe) asics. the first pll in the HMC7044 is designed for low bandwidth configuration using appropriately selected external loop filter components, and internal charge pump bias settings to achiev e less than a few hundred hz bandwidth, typically. the exact bandwidth roll - off points depend on the frequency spectrum of noise that must be attenuated in the system. the first pll locks an external vcxo and provides the clock holdover functions and the r eference frequency to the high performance second pll loop. the combination of the loops provides an excellent clock generation unit with the capability to attenuate incoming reference clock jitter. the second pll loop features two overlapping on - chip vcos that are spi selectable with center frequencies at 2.5 ghz and 3 ghz, respectively. both vcos are designed to have wide tuning ranges for broad output frequency coverage. the desired output frequency is set by the chosen vcxo frequency, vco core (higher o r lower frequency core), and the programmed second pll feedback divider and output channel divider values. the HMC7044 generate s up to seven dclk and sysref clock pairs per the jesd204b interface requirements. the system designer can generate a lower number of dclk and sysref pairs, and configure the remaining output signal paths as desired, either as dclks or additional sysrefs o r other reference clocks with independent phase and frequency adjustment . frequency adjustment can be accomplished by selecting the appropriate output divider values . one of the unique features of the HMC7044 is the independent flexible phase management of each of the 14 channels. using a combination of divider slip - based, digital/coarse and analog/fine delay adjustments, each cha nnel can be programmed to have a different phase offset. the phase adjustment capability allows the designer to offset board flight time delay variations, data converter sample window matching, and meet jesd204b synchronization challenges. the output signa l path design of the HMC7044 is implemented to ensure both linear phase adjustment steps and minimal noise perturbation when ph ase adjustment circuits are turned on. one of the key challenges in jesd204b system design is ensuring the synchronization of data converter frame alignment across the system, from the fpga or dfe to adcs and dacs through a large clock tree that can compri se multiple clock generation and distribution ics. the HMC7044 is specifically designed to offer features to address this chall enge. using the sysref valid interrupt feature, the wait time latency can be reduced in the fpgas. the HMC7044 raises this flag through its gpo port when all counters are set and outputs are at the desired phases. additionally, an external reference - based synchronization feature (sync via pll2 or rf sync only in fanout mode) synchronizes multiple devices, that is, it ensures that all clock outputs start with same rising edge. this operation is achieved by rephasing the sysref control unit deterministi - cally, and then restarting the output dividers with this new desired phase. offering excellent crosstalk, frequenc y isolation, and spurious performance, the device generates independent frequencies in both single - ended and differential formats. the four input reference options allows up to three backup frequency sources, with hitless switching and holdover capabilitie s, supporting system redundancy and uninterrupted operation on reference data and clock failures. the device also features dedicated oscillator fanout mode for best clock isolation, which generates multiple copies of the vcxo clock to be distributed across the board with excellent frequency isolation. both the dclk and sysref clock outputs can be configured to support different signaling standards , including cml, lvds, lvpecl , and lvcmos , and different bias conditions to offset varying board insertion losse s. the outputs can also be programmed for ac or dc coupling and 50 or 100 internal and external termination options. the hm c7044 is programmed via a 3 - wire serial port interface (spi) and powers up with a default configuration that generates valid output frequencies within the vco tuning ranges regardless of whether a reference clock exists. the HMC7044 is offered in a 68 - lead, 10 mm 10 mm, lfcsp package with the exposed pad to ground. note that, throughout this data sheet, multifunction pins, such a s clkin0/rfsyncin, are referred to either by the entire pin name or by a single function of the pin, for example, clkin0, when only that function is relevant. data sheet HMC7044 rev. b | page 24 of 72 detailed block diagr am clkin0/rfsyncin in0 prescaler (1 t o 255) rfsyncin/ rfsyncin clkin0/rfsyncin clkin1/fin clkin1/fin r1 divider (1 t o 65535) phase detec t or charge pum p pll1 r2 divider (1 t o 4095) n2 divider (8 t o 4095) sysref timer los detect holdover n1 divider (1 t o 65535) 2 in1 prescaler (1 t o 255) fin/ fin oscin oscin analog del a y clkin3 clkin3 spi oscout1 oscout1 in3 prescaler (1 t o 255) cpout1 p artial l y integr a ted loo p fi l ter interna l vco 2 vco1 ~ 2500mhz vco2 ~ 3000mhz cpout2 fin/fin oscinbuf clk distribution pa th clkout0 clkout0 sclkout1 sclkout1 clkin2/oscout0 clkin2/oscout0 in2 prescaler (1 t o 255) osc divider 1, 2, 4, 8 divider 1, 2 2 mux mux mux vco mux ext vco ref mux phase detec t or charge pum p pll2 sync/pulsor contro l t o leaf dividers coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) fundamen t a l mode fundamen t a l mode fundamen t a l mode fundamen t a l mode fundamen t a l mode fundamen t a l mode analog del a y coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) analog del a y clkout2 clkout2 sclkout3 sclkout3 clkout8 clkout8 sclkout9 sclkout9 mux mux coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) analog del a y coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) analog del a y sync gpi spi oscinbuf rfsyncin/ rfsyncin fsm mux mux analog del a y coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) fundamen t a l mode fundamen t a l mode fundamen t a l mode fundamen t a l mode analog del a y clkout4 clkout4 sclkout5 sclkout5 clkout10 clkout10 sclkout 1 1 sclkout 1 1 mux mux coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) analog del a y coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) analog del a y mux mux analog del a y coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) fundamen t a l mode fundamen t a l mode fundamen t a l mode fundamen t a l mode ldos analog del a y clkout6 clkout6 sclkout7 sclkout7 clkout12 clkout12 sclkout13 sclkout13 mux mux coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) analog del a y bg a byp1 ldo byp2 ldo byp3 ldo byp4 ldo byp5 ldo byp6 ldo byp7 spi sd at a sclk slen alarm gener a tion device contro l gpio1 gpio2 sync reset gpio3 gpio4 coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) analog del a y mux mux analog del a y coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) coarse digi t a l del a y cycle slip/ sync divider (1 t o 4094) vcxo prescaler (1 t o 255) 13033-032 figure 35 . top level diagram data sheet HMC7044 rev. b | page 25 of 72 dual pll overview the HMC7044 uses a cascade of two plls, referred to as a dua l loop topology. the term dual loop sometimes refer s to other architectures as well; therefore, always refer to the block diagram shown in figure 35 to remove any ambiguity. in this architecture, the first pll (pll1) normally operates as a jitter attenuator. pll1 locks a clean local vcxo to a relatively noisy reference using a very narrow loop bandwidth. the loop bandwidth preserves the average frequency of the reference signal (which is normally correct), while rejecting the majority of its noise. the second pll takes this low noise vcxo and multiplies it up to the vco frequency (in the 2 ghz to 3 ghz range) with very little additive noise. the architecture provides the benefits of an output frequency locked to an input reference signal, while being insensitive to its noise profile. in ics such as the HMC7044 , the vco is then connected to an array of output channels, each with an optional rf divider and phase control. the key feature that distinguishes an ic with jesd204b support is the ability to ensure that all of the outputs with their associated dividers have a user defined phase relationship each and every time, regardless of process, voltage, or temperature . this ability is necessary to support the jesd204b s erdes standard for data converters, but it is also an immensely useful feature in other applications as well, in all forms of arrayed systems and in many test and measurement scenarios. component blocks input pll (pll1) pll1 general description (jitter att enuator) a variety of local clocks, particularly in synchronous networks, derive their timing from a remote node in the network. these reference signals can arrive via a gps or clock data recovery (cdr) receiver, or from a variety of other sources. often, these derived references are relatively poor quality, in terms of spurious content, noise, and reliability. the function of pll1 is to lock a clean vcxo to the average frequency of one of these references and feed it to pll2 to generate a high quality cloc k for local use. in addition, pll1 monitors its active reference for failure and smoothly takes appropriate action, switching to a redundant reference or going into holdover as appropriate. figure 36 shows the architecture of pll1 with a typical frequency configuration. jitter attenuation for the purpose of jitter attenuation, pll1 consists of all the usual components in a pll: a phase/frequency detect or (pfd1), charge pump (cp1), reference divider (r1), and feedback divider (n1). the loop filter is external to provide maximum flexibility, and the loop bandwidth (bw) is normally configured very narrow (20 hz to 500 hz) to filter any jitter and spurious tones coming in from relatively poor references. the noise profile of pll1 is typically dependent on the loop bandwidth, input reference noise, and the vcxo characteristic. the inherent noise sources of pll1 (the pfd, dividers, and charge pump) are not nor mally observable in an application, and are significantly more relaxed compared with pll2. note that the loop filter components on the board are typically configured to produce a certain loop bandwidth, given a fixed pfd rate, charge pump current, and vcxo characteristic. adjusting any of these parameters from their nominal positions affects the loop dynamics, which can be to the advantage of the user (for example, to scale loop bw with charge pump current), but it must not be performed without an analysis of the stability of the loop. analog devices, inc., provides a variety of software tools to design the loop filter and model the effects of any change in parameters. contact analog devices for the latest recommendation. the lock time of pll1 typically take s the longest duration in the clock network, and, aside from any nonlinear slewing, takes approximately 5/pll1_bw (for example, 5 ms for a 1 khz loop bw). fortunately, there are no requirements that pll1 must be locked before proceeding with pll2, output c alibration, and phasing, which normally allows system configuration to continue in parallel while pll1 is settling. HMC7044 data sheet rev. b | page 26 of 72 61.44mhz lockdet pll1 fsm reset rst up down tris ta te rst set r1 cyclesli p force v tune main t ain_holdover los 122.88mhz 38.4mhz lcm dividers t o pll2 cycle sli p detected (t o pll1 fsm) 61.44mhz 9.76mhz d 0 q pfd1 phase error >~4ns? cp1 loo p fi l ter vcxo 122.88mhz n1 com p ar a t or force v tune lockdet t o fsmi lockdet main t ain holdover adc/dac contro l dac 13033-033 figure 36 . pll1 architecture with a typical frequency configuration lock detect the lock detect circuit in both pll1 and pll2 function the same way. they count the number of consecutive clock cycles in which the phase error at the pfd is below a threshold. any phase error above this threshold resets the counter, and the count is restarted. when the count reaches its programmed limit, the lock detect signal is issued and the clock of the counter is gated off to reduce power/coupling until a large phase error res tarts the process. although the pll2 loop bw is relatively well defined, the pll1 loop bw can vary widely in any given application. the spi word, pll1 lock detect timer[4:0] in register 0x0028, configures the pll1 lock detect timer and looks for 2 pll1 lock detect timer[4:0] consecutive lcm clock cycles with a phase - error <~4 ns to issue the lock detect. because the loop bw of pll1 can vary drastically depending on the application, the user must set up the threshold such that 2 pll1 lock detect timer[4:0] lcm periods is on the order of 2 to 4 the loop time constant. for example, for f lcm = 61.44 mhz, and a loop bw of 200 hz, set pll1 lock detect timer[4:0] = 19 or 20. if the value is set much higher, the lock detect circuit takes an unnecessary length of tim e to indicate lock after the phases stabilize. if the value is set much lower (for example, much less than a loop time constant), it can improperly indicate lock during acquisition, which can cause the pll1 finite state machine (fsm) to improperly fall in and out of holdover mode. holdover/reference switching overview when switching between redundant references, or when all references are gone and the pll1 is left open loop, there are often requirements to prevent frequency deviations that can cause downst ream circuits and traffic links to overrun fifos and/or lose lock themselves. pll1 can operate in manual or automode (via the automode reference switching bit). in manual mode, the user selects the active reference using manual mode reference switching[ 1:0] in register 0x0029 and determines whether to go into holdover (via the force holdover bit). in automode, the pll1 fsm uses the loss of signal (los) information, phase error data, lock detect, and configuration data from the spi to determine how to han dle reference interruptions. in either mode, all status indicators are available, but pll1 only takes evasive action in automode. figure 37 shows a sim plified state diagram of the pll1 fsm. during reset, pll1 is held in the initialization (init) state. when reset is deasserted, during the preload state, the enabled reference paths, the reference priority table, and los indicators are examined to select t he best reference, and, on the next cycle, it attempts to lock. after the requisite number of counts has elapsed with low phase error, lock detect is asserted and pll1 transitions to the locked state. when pll1 is locked, a loss of lock, los on the ac tive reference, or a reference switch event initiated by a priority clash transitions the fsm to enter holdover, where it tristates the cp and potentially forces v tune with the holdover dac. when a stable clock is available and other optional conditions are met , the fsm exits holdover. exiting holdover is handled in one of a few different ways, designed to minimize phase/frequency hits during the transition. figure 37 shows a simplification of the pll1 fsm. in the actual implementa tion, the holdover state is broken into a number of subsections corresponding to holdover entry, stable holdover conditions, and holdover exit. the state of the pll1 fsm is always available for a read via the spi (pll1 fsm state[2:0] bits in register 0x0082). data sheet HMC7044 rev. b | page 27 of 72 init reset preload locking lockdet los active ref not lockdet at least one reference ok and best available reference is selected [and phases crossed zero (optional)] [and dac assisted release complete (optional)] or just entered holdover ( HMC7044 data sheet rev. b | page 28 of 72 pll1 holdover entry shortcut when a reference fails, the los circuit takes a number of lcm clock cycles to recognize the problem and to request the pll1 fsm enter holdover and tristate the cp. by that time, if one of the missing edges is needed to trigger the r divider output, the pfd and cp have already saturated, pulling current out of the loop filter for these cycles, and disturbing the holdover frequency. the probabilit y of this happening decreases as the pfd rate decreases relative to f lcm , but it is not eliminated. the HMC7044 includes a uniq ue feature to prevent this type of frequency runaway. a sensor watches the up/down pulses from the pfd (see figure 35 ). when locked, the pulse width is small, based on any small signal error, pfd/cp offset, and the reset delay of the pfd. if the device is in the locked state and has a phase error that is larger than expected (~4 ns), it is a sign that the reference has failed, and the device immediately tristates the pump, reducing the amount of time charge can be extracted from the loop from about five lcm cycles (162 ns at 30.72 mhz) to <4 ns. this error indication also invalidates the lock detect. when the fsm acknowledges the issue, it holds the cp in tristate. when using the optional dac - based holdover, the fsm instructs the adc/dac that is tracking the v tune voltage to switch from sense mode to force mode, holding it steady to within 1 lsb (about 20 mv or 0.4 ppm) until the HMC7044 senses a stable reference and transitions ou t of holdover. pll1 holdover steady state when in the holdover state, the user has the following two options: ? tristate the cp ? tristate the cp and engage the holdover dac when in tristate mode, the HMC7044 has a very high impedance charge pump output (~10 g). this output is normally an insignificant contributor to pll1 v tune leakage, which is determined primarily by the on - board l oop filter components and the vcxo tuning port. this mode allows the tuning voltage to maintain itself for significant periods while in holdover. to accommodate indefinite periods in holdover, or to ensure v tune is driven and not susceptible to drift, the second option (set via the holdover uses dac bit in register 0x0029, bit 2) forces the v tune voltage to its time averaged value, obtained by low - pass filtering the adc value while the pll is reporting lock. the holdover sensing adc and the driving dac are seven bits each, and have an lsb of approximately 19 mv. pll1 holdover exit the transition out of holdover can happen in three ways and is controlled by the holdover exit criteria[1:0] bits and the holdover exit action[1:0] bits in register 0x0016 (see the control register map bit descriptions section for details), which describes the steps that the fsm takes as the HMC7044 exits holdover and acquires lock. the recommended methods are as follows: ? wait for zero phase error (no divider reset): wait for los = 0 and low phase error at pfd (holdover exit criteria[1:0] = 1 , holdover exit action[1:0] = 1) ? resetting the dividers: wait for los = 0 and reset the r1/n2 dividers (holdover exit criteria[1:0] = 0, holdover exit action[1:0] = 0) ? dac assisted release: wait for los = 0, reset r1 /n2, and configure for dac assisted release (holdover exit criteria[1:0] = 0, holdover exit action[1:0] = 3) wait for zero phase error while the cp is still in tristate, the fsm monitors the pdf for a cycle slip indication as the candidate reference and v cxo signal cross each other. the crossing of the reference and vcxo phases eventually occurs but can take a long time, as determined by the inherent frequency error due to an imperfect holdover. just after a cycle slip event, the phase error at the pfd is at its minimum value, and there is minimal glitch as the pll reacquires. figure 38 shows an example where the reference is removed and pll1 goes into tristate - based holdover. after approximately 7 sec, the reference is restored and, about a second later, the phases cross an d the pll reacquires, all with less than 0.15 ppm of deviation from the original frequency value. 1.0 0.8 0.2 ?0.4 ?1.0 1 4 time (seconds) 7 9 10 13033-035 0.6 0 frequency deviation from nominal (ppm) ?0.6 0.4 ?0.2 ?0.8 0 2 5 3 6 8 7 5 , 6 7 $ 7 ( + 2 / ' 2 9 ( 5 0 2 ' ( 6 ( & |